【主講人】Dr. Tse-Yu Yeh, VP of Silicon Engineering of Rivos Inc.
【講題】 A Journey of an Architect from Software to Chip Design
【時間】 2022年11月25日 13:10-14:40
【地點】成功大學電機系館 迅慧講堂
【報名連結】11月28日中午前至http://bit.ly/3UT8pFh報名
Dr. Tse-Yu Yeh is the VP of Silicon Engineering of Rivos Inc. Rivos is a multi-national start-up company targeting towards integrated hardware, software, and chip design for server applications in data analytics and machine learning. Prior to his position at Rivos Inc., he was the Senior Director of the high performance CPU design group at Apple. He managed the team delivered the high performance CPUs in M series of SOCs and A series of SOCs. He built the CPU design team up from the initial team acquired from P.A. Semi. At P.A. Semi he was the Senior Director of CPU architecture and SOC verification. He also worked at Broadcom as the senior manager in the Broadband processor division and the CPU architect at SiByte. He started his career at Intel as the IA-64 front end architect, microarchitect, and verification manager.
He received his PhD from the Electrical Engineering and Computer Science Department at the University of Michigan. His research focused on the out of order execution and branch prediction. In 2007, one of his papers on Two-level branch prediction published in 1992 was selected to be among the most influential papers in International Symposium of Computer Architecture.
【講題】 A Journey of an Architect from Software to Chip Design
【時間】 2022年11月25日 13:10-14:40
【地點】成功大學電機系館 迅慧講堂
【報名連結】11月28日中午前至http://bit.ly/3UT8pFh報名
Dr. Tse-Yu Yeh is the VP of Silicon Engineering of Rivos Inc. Rivos is a multi-national start-up company targeting towards integrated hardware, software, and chip design for server applications in data analytics and machine learning. Prior to his position at Rivos Inc., he was the Senior Director of the high performance CPU design group at Apple. He managed the team delivered the high performance CPUs in M series of SOCs and A series of SOCs. He built the CPU design team up from the initial team acquired from P.A. Semi. At P.A. Semi he was the Senior Director of CPU architecture and SOC verification. He also worked at Broadcom as the senior manager in the Broadband processor division and the CPU architect at SiByte. He started his career at Intel as the IA-64 front end architect, microarchitect, and verification manager.
He received his PhD from the Electrical Engineering and Computer Science Department at the University of Michigan. His research focused on the out of order execution and branch prediction. In 2007, one of his papers on Two-level branch prediction published in 1992 was selected to be among the most influential papers in International Symposium of Computer Architecture.